Conventional asynchronous static random-access memories (SRAMs) rely upon carefully controlled memory access signal delays for proper operation. Changing operating conditions and other factors can cause variations in signal timing that can create memory write errors. The following background is provided to more clearly describe this problem.
Asynchronous SRAMs are widely used high speed memory devices. The operation of asynchronous SRAMs is well known and therefore is only briefly described herein. FIG. 1 illustrates a block diagram of an asynchronous SRAM 100. The controller 122 initiates a memory operation by asserting a chip enable signal 101 and supplying address signals A0-AN (corresponding to 2.sup.N+1 memory locations) designating the address of a memory location where the operation is to be performed. If the memory operation is a write operation, the controller 122 supplies the data to be written to the address memory location via the bi-directional input/output line I/O0-I/OK (corresponding to K+1 bit memory words). If the memory operation is a read operation, the stored information from the addressed location is read out from the same bi-directional input/output lines I/O0-I/OK. The memory 100 also provides connections for external power supply (VCC) and ground (GND) signals.
The heart of the memory 100 is the memory array 112, which consists of static memory cells, each capable of storing one bit of data, arranged in rows and columns. In the conventional manner, all of the cells in one row are energized for a memory operation (either a read or a write) by a word line WL uniquely associated with that row. A memory operation cannot be performed unless the word line associated with the target row of cells is activated.
At least a subset of the cells in a row (typically all of the cells that store data for one memory word) can be accessed simultaneously for a given memory operation via the bit lines BL. When the memory operation is a read, the bit lines BL are coupled to sense amplifiers in the column I/O 120 that sense the data stored in the corresponding cells of the row whose word line WL is active. When the memory operation is a write, the bit lines BL carry the signals used to program the corresponding cells of the row associated with the active word line.
The control circuit 116 controls the other blocks of the memory 100 in response to the chip enable signal 101 and control signals 103. Control signals 103 may include a write signal (WRTB) to initiate a write operation to the memory. Depending on the operation to be performed, the control circuit issues the appropriate control signals 117a, 117b to the decoder 114 and the I/O data circuit 118, respectively.
Regardless of whether the memory operation is a write or a read, the decoder 114 decodes the address signals A0-AN and activates the word line WL of the row that includes the memory word that is the target of the current memory operation.
If the operation is a write, the I/O data circuit 118 buffers the input data signals I/O0-I/OK and outputs the buffered data to the column I/O 120 via the bi-directional data bus 119. The column I/O 120 then latches the input signals in parallel onto the corresponding bit lines BL0-BLK. The signals on the bit lines BL0-BLK are used to program the cells composing the word whose word line was activated for the current operation by the decoder 114.
If the operation is a read, sense amplifiers (SA) in the column I/O 120 sense the signals on the respective bit lines BL, convert the sensed signals into binary (e.g., high or low) voltages that represent the programmed state of the addressed word and output the word's bit values to the I/O data circuit 118 via the bi-directional bus 119. The output data are buffered by the I/O data circuit 118 and latched onto the bi-directional data lines I/O0-I/OK for use by the controller 122.
FIG. 2 illustrates a conventional control circuit for the memory of FIG. 1. An X address signal Ax 250 is coupled to a decoder 210 and an address transition detection (ATD) circuit 212. The output of decoder 210 drives a word line WL 260 which selects a memory cell 224. Similarly, a Y address signal Ay 252 is coupled to a decoder 218 and to an ATD circuit 232. The output of decoder 218 is a column select signal COL 258 which couples a corresponding bit/bit-bar line pair BL/BL to a local I/O bus 264.
If memory array 112 is partitioned into blocks, a Z address signal Az 253 is coupled to a decoder 245 and at ATD circuit 241. The output of decoder 245 is a block select BLK signal 259 used to enable a particular block for a write or read.
X address signal Ax, Y address signal Ay and Z address signal Az each typically comprise a plurality of address lines. Similarly, typically decoder 210 has a plurality of word line outputs, decoder 218 has a plurality of column select outputs and decoder 245 has a plurality of block select outputs. These decoder outputs access an array of memory cells 224. For simplicity, only one small part of this array is illustrated in FIG. 2 with a single memory cell 224.
ATD circuits 212, 232 and 241 each output a pulse whenever a rising edge or falling edge transition occurs in their address signal input. Therefore, when address signals Ax, Ay or Az change, the corresponding ATD circuit outputs a pulse to equalization circuit 242. In response, equalization circuit 242 asserts EQ signal 256 to precharge and equalize the bit/bit-bar line pair BL/BL and local I/O bus 264 using precharge transistors (not shown) and transistor 230 (which may be eliminated in some implementations). This operation prevents the data stored on the BL/BL pair from being further written to any memory cell in the column. It also prepares the BL/BL pair and local I/O bus for a subsequent write or read operation.
Write circuit 239, comprising transistors 236 and 238, couples data line pair D/D (266/288) to local I/O bus 264. Write circuit 239 enables data defined by pair D/D to be written to a memory cell 224 during a write operation.
FIG. 2A illustrates a timing diagram for a write operation for the conventional control circuit of FIG. 2. At the beginning of the write operation, a new address A.sub.1 comprising X address signal Ax, Y address signal Ay, and Z address signal Az is received by memory 100.
Some time after the change of address occurs, WL signal 260, COL signal 258 and BLK signal 259 transition high in response to the receipt of address A1. The delay between the change of address and the assertion of WL signal 260, COL signal 258 and BLK signal 259 is caused by the delay of decoders 210, 218 and 245 and any other delays in the circuit path from the pins for address signals Ax, Ay and Az to the WL, COL and BLK lines. The delay for the three signals is shown as equal but may be different.
Some time after the change of address occurs, a write bar (WRTB) signal 254 is asserted. WRTB is an active low signal. In response, a write pulse (WPL) signal 262 transitions high a short time later. The delay between the assertion of WRTB signal 254 and the transition of WPL signal 262 is caused by the delay of a buffer 246, a NAND gate 270, an inverter 271, and any other delays in the circuit path from the pin for WRTB signal 254 to WPL signal 262. The assertion of WPL signal 262 causes transistors 236 and 238 of write circuit 239 to become enabled, allowing data defined by data lines pair D/D to be written to selected memory cell 224.
After a time sufficient to write the data to memory cell 224, WRTB signal 254 is deasserted. In response, WPL signal 262 transitions low a short time later, disabling write circuit 239.
At about the same time or shortly after WRTB signal 254 is deasserted, address A may change from address A.sub.1 to address A.sub.2. The period of time that address A.sub.1 is held after WRTB signal 254 is deasserted is called the write address hold time, or t.sub.HA. In response to the new address, WL signal 260, COL signal 258 and BLK signal 259 are deasserted and a different word line, column select line and block select line (not shown) are asserted. At this point, a new memory operation has begun.
FIG. 2A shows the desired timing relationships between the various signals within memory 100. In this figure, t.sub.HA is positive with address A held constant until after WRTB signal 254 is deasserted. A positive t.sub.HA ensures that the selected word line, column select line and block select line do not change while WPL signal 262 is still asserted. If the address changes to A.sub.2 before WRTB signal 254 is deasserted (i.e., t.sub.HA is negative), however, the new word line, column select line and block select line corresponding to address A.sub.2 may turn on while WPL signal 262 is still asserted. Because write circuit 239 would still be enabled, data would be improperly written to address A.sub.2. This condition may even occur with a small positive t.sub.HA due to signal timing deviations caused by varying processing, temperature or voltage conditions. Therefore, memory write errors may occur if memory 100 is provided with address signals having a very small or negative write address hold time t.sub.HA.
However, systems employing such asynchronous memories are being operated at progressively higher clock speeds that dictate increasingly tight timing constraints. As a result, these systems typically provide the asynchronous memories with short write address hold times t.sub.HA, sometimes approaching zero nanoseconds.
In view of the foregoing, there is a need for a circuit in an asynchronous SRAM that minimizes the write address hold time required to prevent data from being written to incorrect addresses in the memory.